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Preliminary Technical Data
PERFORMANCE FEATURES Complete Single Device Multi-Port Internet Gateway Processor (No External Memory Required) Implements Sixteen Modem Channels or Forty Voice Channels in One Package Each DSP Can Implement two V.34/V.90 Data/Fax Modem Channels (includes Datapump and Controller) Low Power Version: 640 MIPS Sustained Performance, 12.5 ns Instruction Time @ 1.9 Volts nominal (internal) Open Architecture Extensible to Voice-over-Network (VoN) and Other Applications Low Power Dissipation, 25 mW (typical) per Channel Powerdown Mode Featuring Low CMOS Standby Power Dissipation
MultiPort Internet Gateway Processor ADSP-21MOD980N
INTEGRATION FEATURES ADSP-2100 Family Code-Compatible, with Instruction Set Extensions 16 Mbits of On-Chip SRAM, Configured as 9 Mbits of Program Memory and 7 Mbits of Data Memory Dual-Purpose Program Memory, for Both Instruction and Data Storage 352-Ball PBGA with a 35mm 35mm footprint SYSTEM CONFIGURATION FEATURES 16-Bit Internal DMA Port for High-Speed Access to On-Chip Memory (Mode-Selectable) Programmable Multichannel Serial Port Supports 24/32 Channels Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Separate Reset Pins for Each Internal Processor
21m od980N
Host IDMA SPORT0 SPORT1
2188N DSP 1
2188N DSP 2
2188N DSP 3
2188N DSP 4
2188N DSP 5
2188N DSP 6
2188N DSP 7
2188N DSP 8
CONTROL
Figure 1. MOD980N MultiPort Internet Gateway Processor Block Diagram
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. One Technology Way, P .O.Box 9106, Norwood, MA 02062-9106, U.S.A. Tel:781/329-4700 World Wide Web Site: http://www.analog.com Fax:781/326-8703 (c)Analog Devices,Inc., 2001
PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
GENERAL DESCRIPTION
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MODEM SOFTWARE
The ADSP-21MOD980N is a multi-port Internet gateway processor optimized for implementation of a complete V.34/V.90 digital modem. All datapump and controller functions can be implemented on a single device, offering the lowest power consumption and highest possible modem port density. The ADSP-21MOD980N combines the ADSP-2100 Family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The ADSP-21MOD980N integrates 16 Mbits of on-chip memory, configured as 384 Kwords (24-bit) of program RAM, and 448 Kwords (16-bit) of data RAM. Power-down circuitry is also provided to reduce the average and standby power consumption of equipment which in turn reduces equipment cooling requirements. The ADSP-21MOD980N is available in a 35 mm x 35 mm, 352-lead PBGA package. Fabricated in a high-speed, low-power, CMOS process, the ADSP-21MOD980N operates with a 12.5 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-21MOD980N's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, the ADSP-21MOD980N can: * * * * * * * * * Generate the next program address Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computational operation Receive and transmit data through the two serial ports Receive and/or transmit data through the internal DMA port Receive and/or transmit data through the byte DMA port Decrement timer
The following software is available as object code from Analog Devices Inc. * * ADSP-21mod Family Dynamic Internet Voice AccessTM (DIVA) Voice Over Network Solution. ADSP-21mod980-210N Multiport Internet Gateway Processor Modem Solution.
A complete system implementation requires the ADSP-21MOD980N device plus modem or voice software. The modem software executes general modem control, command sets, error correction, and data compression, data modulations (for example, V.34 and V.90), and host interface functions.The host interface allows system access to modem statistics, such as call progress, connect speed, retrain count, symbol rate, and other modulation parameters. The modem datapump and controller software reside in on-chip SRAM and do not require additional memory. You can configure the ADSP-21MOD980N dynamically by downloading software from the host through the 16-bit IDMA interface. This SRAM-based architecture provides a software upgrade path to other applications, such as voice-over-IP, and to future standards.
DEVELOPMENT SYSTEM
Analog Devices' wide range of software and hardware development tools supports the ADSP-218x N Series. The DSP tools include an integrated development environment (IDE), an evaluation kit, and a serial port emulator. VisualDSP(R) is an integrated development environment, allowing for fast and easy development, debug and deployment. The VisualDSP project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder); a linker; a loader; a cycle-accurate, instruction-level simulator; a C compiler; and a C run-time library that includes DSP and mathematical functions. Debugging both C and assembly programs with the VisualDSP debugger, programmers can: * View mixed C and assembly code (interleaved source and object information) * Insert break points * Set conditional breakpoints on registers, memory, and stacks * Trace instruction execution * Fill and dump memory * Source level debugging
This takes place while the processor continues to:
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ADSP-21MOD980N
The VisualDSP IDE lets programmers define and manage DSP software development. The dialog boxes and property pages let programmers configure and manage all of the ADSP-218x development tools, including the syntax highlighting in the VisualDSP editor. This capability controls how the development tools process inputs and generate outputs. The ADSP-218x EZ-ICE (R) Emulator provides an easier and more cost-effective method for engineers to develop and optimize DSP systems, shortening product development cycles for faster time-to-market. The ADSP-21MOD980N integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-21MOD980N device need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs.The EZ-ICE performs a full range of functions, including: * In-target operation * Up to 20 breakpoints * Single-step or full-speed operation * Registers and memory values can be examined and altered * PC upload and download functions * Instruction-level emulation of program booting and execution * Complete assembly and disassembly of instructions * C source-level debugging
ADDITIONAL INFORMATION
This data sheet provides a general overview of ADSP-21MOD980N functionality. For specific information about the modem processors, refer to the ADSP-2188N data sheet. For additional information on the architecture and instruction set of the modem processors, refer to the ADSP-2100 Family User's Manual (3rd edition). For more information about the development tools, refer to the ADSP-2100 Family Development Tools Data Sheet.
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PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
ARCHITECTURE OVERVIEW
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Figure 2 on page 4 is a functional block diagram of the ADSP-21MOD980N. It contains eight independent digital signal processors.
DATA< 23:8>, A<0 >
17 IAD <15:0>, IDM A CNTL 20 3 20
CLKIN IAD<15:0>, IDM A CNTL PF<0:2>/M OD E A:C
2188N DSP 1
2188N DSP 2
2188N
2188N
2188N
2188N DSP 6
2188N DSP 7
2188N DSP 8
DSP 3
DSP 4
DSP 5
4 SPORT0A SPORT1 EMULATOR 4 8
4 SPORT0B
SIGNALS RO UTED TO EACH RESPECTIVE DIE 8 8 8 8 CLKOUT <8:1> 8 EE <8:1> 8 IS <8:1> 8 TFS0 <8:1> DT1 <8:1> INTERRUPTS < 8:1> 8 32
IDM A CNTL = IAL, IRD, IW R, IACK INTERRUPTS = IRQE (PF4), IRQL 0(PF5), IRQL1(PF6), IRQ2(PF7)
BR <8:1> BG <8:1> RESET <8:1>
EMULATOR
= EMS, EINT, ELIN, EBR, EBG, ECLK ELOUT, ERESET
SPORT0A, SPO RT 0B = RFS0, DR0, DT0, SCKL0 SPORT1 = RFS1, TFS1, DR1, SCKL1
NOTE : 1. PW D AND PF3/MODE D ARE TIED HIGH
SUBTO TAL = 177 SIG NAL BALLS 109 GND 44 VDDINT 22 VDDEXT
SUBTO TAL = 175 POW ER BALLS TOTAL = 352 BALLS
Figure 2. ADSP-21MOD980N Functional Block Diagram
Every modem processor has: * * * * A DSP core 256K bytes of RAM Two serial ports An IDMA host.
accessed through a single external pin. Other signals remain separate and they are accessed through separate external pins for each processor. The arrangement of the eight modem processors in the ADSP-21MOD980N makes one basic configuration possible: a slave configuration. In this configuration, the data pins of all eight processors connect to a single bus structure.
The signals of each modem processor are accessed through the external pins of the ADSP-21MOD980N. Some signals are bussed with the signals of the other processors and are 4
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PRELIMINARY TECHNICAL DATA
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ADSP-21MOD980N
All eight modem processors have identical functions and have equal status. Each of the modem processors is connected to a common IDMA bus and each modem processor is configured to operate in the same mode (see the slave mode and the memory mode descriptions in "Memory Architecture" on page 10). The slave mode is considered to be the only mode of operation in the ADSP-21MOD980N modem pool.
SERIAL PORTS
The ADSP-21MOD980N has a multichannel serial port (SPORT) connected to each internal digital modem processor for serial communications. The following is a brief list of ADSP-21MOD980N SPORT features. For additional information on the internal Serial Ports, refer to the ADSP-2100 Family User's Manual. Each SPORT: * * * is bidirectional and has a separate, double-buffered transmit and receive section. can use an external serial clock or generate its own serial clock internally. has independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulse widths and timings. supports serial data word lengths from 3 to 16 bits and provides optional A-law and -law companding according to CCITT recommendation G.711. receive and transmit sections can generate unique interrupts on completing a data word transfer. can receive and transmit an entire circular buffer of data with one overhead cycle per data word. An interrupt is generated after a data buffer transfer.
*
* *
A multichannel interface selectively receives and transmits a 24 or 32 word, time-division multiplexed, serial bitstream.
PIN DESCRIPTIONS
The ADSP-21MOD980N is available in a 352-lead PBGA package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. Table on page 6 lists the pin names and their functions. In cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.
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PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
Table 1. Common Mode Pins Pin Name(s) # of Pins Input/Output Function
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RESET BR BG IRQ2 / PF7 IRQL1 / PF6 IRQL0 / PF5 IRQE / PF4 Mode C / PF2 Mode B / PF1 Mode A / PF0 CLKIN CLKOUT SPORT VDD and GND EZ-Port
1
8 8 8 8 8 8 8 8 8 8 8 1 1 1 1 1 1 1 8 28 175 16
I I O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I O I/O I I/O
Processor Reset Input Bus Request Input Bus Grant Output Edge- or Level-Sensitive Interrupt Request1 Programmable I/O Pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Edge-Sensitive Interrupt Requests1 Programmable I/O Pin Mode Select Input - Checked Only During RESET Programmable I/O Pin During Normal Operation Mode Select Input - Checked Only During RESET Programmable I/O Pin During Normal Operation Mode Select Input - Checked Only During RESET Programmable I/O Pin During Normal Operation Clock Input Processor Clock Output Serial Port I/O Pins2 Power and Ground For Emulation Use
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the ADSP-21MOD980N will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. SPORT configuration determined by the ADSP-21MOD980N System Control Register. Software configurable.
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MEMORY INTERFACE PINS
The ADSP-21MOD980N modem pool is used in Slave Mode. In Slave Mode, the Modem Processors operate in host configuration. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the modem pool is running. See the "Memory Architecture" section for more information.
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ADSP-21MOD980N
Table 2. Host Pins (Mode C = 1) Modem Processors 1-8 Pin Name # of Pins Input/ Output Function
IRQE is edge sensitive. The priorities and vector addresses of all interrupts are shown in Table on page 7. When the modem pool is reset, interrupt servicing is disabled.
Table 3. Interrupt Priority and Interrupt Vector Addresses Source Of Interrupt Interrupt Vector Address (Hex)
IAD[15:0] A0
321 1
I/O O
IDMA Port Address/Data Bus Address Pin for External I/O, Program, Data, or Byte access Data I/O Pins for Program, Data Byte and I/O spaces IDMA Write Enable IDMA Read Enable IDMA Address Latch Pin IDMA Selects IDMA Port Acknowledge Configurable in Mode D; Open Drain
RESET (or Power-Up with PUCR = 1) Power Down (Nonmaskable) IRQ2 IRQL1 IRQL0 SPORT0 Transmit SPORT0 Receive IRQE BDMA Interrupt SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 Timer
LOW POWER OPERATION
0x0000 (Highest Priority) 0x002C 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 (Lowest Priority)
D[23:8]
16
I/O
IWR IRD IAL IS IACK
21 21 21 8 21
I I I I O
1
There are two distinct IAD buses. One addresses DSPs 1-4 and the other communicates with DSPs 5-8. See Figure 2 for details.
INTERRUPTS
The interrupt controller allows each modem processor in the modem pool to respond individually to eleven possible interrupts and RESET with minimum overhead. The ADSP-21MOD980N provides four dedicated external interrupt input pins, IRQ2, IRQL1, IRQL0, and IRQE (shared with the PF[7:4] pins) for each modem processor. The ADSP-21MOD980N also supports internal interrupts from the timer, the byte DMA port, the serial port, software, and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power down and RESET). The IRQ2, IRQ1, and IRQ0 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are level-sensitive and
The ADSP-21MOD980N has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are: * * * Power Down Idle Slow Idle
The CLKOUT pin may also be disabled to reduce external power dissipation.
POWER DOWN
The ADSP-21MOD980N modem pool has a low power feature that lets the modem pool enter a very low power dormant state through software control. Here is a brief list
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PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
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of power-down features. Refer to the ADSP-2100 Family User's Manual, "System Interface" chapter, for detailed information about the power-down feature. * Quick recovery from power down. The modem pool begins executing instructions in as few as 200 CLKIN cycles. Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during power down without affecting the lowest power rating and 200 CLKIN cycle recovery. Power down is initiated by the software power-down force bit. Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. Context clear/save control allows the modem pool to continue where it left off or start with a clean context when leaving the power down state. The RESET pin also can be used to terminate power down.
*
When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the modem pool's reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the modem pool takes to come out of the idle state (a maximum of n cycles).
SYSTEM CONFIGURATION
*
*
*
IDLE
When the ADSP-21MOD980N is in the Idle Mode, the modem pool waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle steals still occur.
SLOW IDLE
Figure on page 9 shows the hardware interfaces for a typical multichannel modem configuration with the ADSP-21MOD980N. Other system design considerations such as host processing requirements, electrical loading, and overall bus timing must all be met. A line interface can be used to connect the multichannel subscriber or client data stream to the multichannel serial port of the ADSP-21MOD980N. The IDMA port of the ADSP-21MOD980N is used to give a host processor full access to the internal memory of the ADSP-21MOD980N. This lets the host dynamically configure the ADSP-21MOD980N by loading code and data into its internal memory. This configuration also lets the host access server data directly from the ADSP-21MOD980N's internal memory. In this configuration, the Modem Processors should be put into host memory mode where Mode C = 1, Mode B = 0, and Mode A = 1.
The IDLE instruction is enhanced on the ADSP-21MOD980N to let the modem pool's internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is: IDLE (n); where n = 16, 32, 64, or 128. This instruction keeps the modem pool fully functional, but operating at the slower clock rate. While it is in this state, the modem pool's other internal clock signals, such as SCLK, CLKOUT, and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction. When the IDLE (n) instruction is used, it effectively slows down the modem pool's internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-21MOD980N will remain in the idle state for up to a maximum of n modem pool cycles (n = 16, 32, 64, or 128) before resuming normal operation.
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ADSP-21MOD980N
T1/E1 LINE INTERFACE
T1/E1 LINE INTERFACE
T1/E1 LINE INTERFACE
SPORT
SPORT
SPORT
21mod980N
21mod980N
21mod980N
ST/CNTL IDMA
ST/CNTL IDMA
ST/CNTL IDMA
Figure 3. Multichannel Modem Configuration CLOCK SIGNALS
The ADSP-21MOD980N is clocked by a TTL-compatible clock signal that runs at half the instruction rate; a 40 MHz input clock yields a 12.5 ns processor cycle, which is equivalent to 80 MHz. Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. The clock input signal is connected to the processor's CLKIN input. REV. PrB 6/2001
The CLKIN input cannot be halted, changed during operation, or operated below the specified frequency during normal operation. The only exception is while the processor is in the power down state. For additional information, refer to Chapter 9, ADSP-2100 Family User's Manual for a detailed explanation of this power down feature.
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A clock output (CLKOUT) signal is generated by the processor at the processor's cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register.
RESET
* *
Figure on page 11 shows Data Memory Table on page 11 shows the generation of address bits based on the DMOVLAY values. Access to external memory is not available
PM M O D E B = 0 AL W A Y S AC C E SS IB L E AT A D DR E S S 0x0000 - 0x1FFF
The RESET signals initiate a reset of each modem processor in the ADSP-21MOD980N. The RESET signals must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to let the internal clocks stabilize. If RESETs are activated any time after power up, the clocks continue to run and do not require stabilization time. The power-up sequence is defined as the total time required for the oscillator circuits to stabilize after a valid VDD is applied to the processors, and for the internal phase-locked loops (PLL) to lock onto the specific frequency. A minimum of 2000 CLKIN cycles ensures that the PLLs have locked, but this does not include the oscillators' start-up time. During this power-up sequence, the RESET signals should be held low. On any subsequent resets, the RESET signals must meet the minimum pulse width specification, tRSP. The RESET input contains some hysteresis; however, if you use an RC circuit to generate your RESET signals, the use of an external Schmidt triggers are recommended. The RESET for each individual modem processor sets the internal stack pointers to the empty stack condition, masks all interrupts and clears the MSTAT register. When a RESET is released, if there is no pending bus request and the modem processor is configured for booting, the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes.
MEMORY ARCHITECTURE
AC C E SS IB L E W H EN PM O VL AY = 0
0x2000 0x3FFF 0x2000 0x3FFF 0x2000 0x3FFF 0x2000 0x3FFF 0x2000 0x3FFF
AC C E SS IB L E W H EN PM O VL AY = 4 AC C E SS IB L E W H EN PM O VL AY = 5 AC C E SS IB L E WHEN PM O VL AY = 6 IN T ER N A L MEMORY AC C E SS IB L E WHEN PM O VL AY = 7
PROGRAM MEMORY MODE B=0 ADDRESS 0x3FFF 8K INTERNAL PMOVLAY = 0, 4, 5, 6, 7
0x2000 0x1FFF
The ADSP-21MOD980N provides a variety of memory and peripheral interface options for Modem Processor 1. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to the following figures and tables for PM and DM memory allocations in the ADSP-21MOD980N. The ADSP-21MOD980N modem pool operates in one memory mode: Slave Mode. The following figures and tables describe the memory of the ADSP-21MOD980N: * * Figure on page 10 shows Program Memory Table on page 10 shows the generation of address bits based on the PMOVLAY values
8K INTERNAL 0x0000
Figure 4. Program Memory Map Table 4. PMOVLAY bits PMOVLAY Memory A13 A[12:0]
0, 4, 5, 6, 7
Internal
Not Applicable
Not Applicable
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DA T A M EM O RY
Table 5. DMOVLAY bits
AL W A Y S AC C E SS IB L E AT A D DR E S S 0x2000 - 0x3F F F
DMOVLAY
Memory
A13
A[12:0]
0, 4, 5, 6, 7, 8
0x0000 - 0x1F F F 0x0000 - 0x1F F F AC C E SS IB L E W H EN DM O VL AY = 0 AC C E SS IB L E W H EN DM O VL AY = 4 AC C E SS IB L E W H EN DM O VL AY = 5 IN T ER N A L MEMORY AC C E SS IB L E W H EN DM O VL AY = 6 AC C E SS IB L E W H EN DM O VL AY = 7 AC C E SS IB L E W H EN DM O VL AY = 8 0x0000 - 0x1F F F 0x0000 - 0x1F F F 0x0000 - 0x1F F F 0x0000 - 0x1F F F
Internal
Not Applicable
Not Applicable
MEMORY MAPPED REGISTERS (NEW TO THE ADSP-21MOD980N)
The ADSP-21MOD980N has three memory mapped registers that differ from other ADSP-21xx Family DSPs. See "Waitstate Control Register" on page 11. See "Programmable Flag & Composite Select Control Register" on page 12. See "System Control Register" on page 12. The slight modifications to these registers provide the ADSP-21MOD980N's waitstate and BMS control features.
DATA MEMORY 32 MEMORY MAPPED REGISTERS INTERNAL 8160 WORDS 8K INTERNAL DMOVLAY = 0, 4, 5, 6, 7, 8
ADDR 0x3FFF 0x3FE0 0x3FDF 0x2000 0x1FFF
Figure 5. Data Memory Map
15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 D M (0x3 F F E )
.
D W A IT
IO W AIT 3
IO W AIT 2
IO W AIT 1
IO W AIT 0
W ait S tate M o d e S ele ct 0 = N o rm al m o d e (P W AIT , D W AIT , IO W A IT 0 -3 = N w ait states, ran g in g fro m 0 to 7) 1 = 2N + 1 m o de (P W AIT , D W AIT , IO W AIT 0 -3 = 2N + 1 w ait states, ran g in g fro m 0 to 15 )
Figure 6. Waitstate Control Register
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PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
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15 14 13 12 11 10 9 1 1 1 1 1 0 1
8 1
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0 DM(0x3FE6)
BMWAIT
CMSSEL 0 = Disable CMS 1 = Enable CMS
PFTYPE 0 = Input 1 = Output
(where bit: 11-IOM, 10-BM, 9-DM, 8-PM)
Figure 7. Programmable Flag1 & Composite Select Control Register
1
Since they are multiplexed within the ADSP-21MOD980N, PF[2:0] should be configured as an output for only one processor at a time. Bit [3] of DM (0x3FE6) must also be 0 to ensure that PF[3] is never an output.
15 0
14 0
13 0
12 0
11 0
10 1
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 1
1 1
0 1 D M (0x3F F F )
R e se rve d S et To 0
S P O R T 0 E n ab le 0 = D isa b le 1 = E n ab le
RES ERVE D S ET T O 0 P W A IT P ro g ram M em o ry W ait S tates D is ab le B M S 0 = E n ab le B M S 1 = D isa b le B M S , exc ep t w h en m e m o ry stro be s are th ree-stated
S P O R T 1 E n ab le 0 = D isa b le 1 = E n ab le S P O R T 1 C o nfigu re 0 = F I, F O , IR Q 0, IR Q 1, S C L K 1= S P O R T 1
Figure 8. System Control Register
Table 6. ADSP-21MOD980N Mode of Operation MODE C MODE B MODE A Booting Method
IDMA feature is used to load internal memory as desired. Program execution is held off until internal program memory location 0x0000 is written to. Chip is configured in Slave Mode.1 IACK requires external pulldown.2
1
0
1
1 2
Considered standard operating settings. These configurations simplify your design and improve memory management. IDMA timing details and the correct usage of IACK are described in the ADSP-2100 Family User's Manual.
SLAVE MODE
INTERNAL MEMORY DMA PORT (IDMA PORT)
This section describes the Slave Mode memory configuration of the Modem Processors.
The IDMA Port provides an efficient way for a host system and the ADSP-21MOD980N to communicate. The port is used to access the on-chip program memory and data memory of each modem processor with only one processor cycle per word overhead. The IDMA port cannot be used, how6/2001 REV. PrB
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ADSP-21MOD980N
ever, to write to the processor's memory-mapped control registers. A typical IDMA transfer process is described as follows: 1. 2. Host starts IDMA transfer Host uses IS and IAL control lines to latch either the DMA starting address (IDMAA) or the PM/DM OVLAY selection into the processor's IDMA control registers. If IAD [15] = 1, the value of IAD [7:0] represents the IDMA overlay: IAD[14:8] must be set to 0. If IAD [15] = 0, the value of IAD [13:0] represents the starting address of internal memory to be accessed and IAD [14] reflects PM or DM for access. 1. 2. Host uses IS and IRD (or IWR) to read (or write) processor internal memory (PM or DM). Host ends IDMA transfer.
specifies an on-chip memory location, the destination type specifies whether it is a DM or PM access. The falling edge of the address latch signal latches this value into the IDMAA register. Once the address is stored, data can then be either read from, or written to, the ADSP-21MOD980N's on-chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-21MOD980N that a particular transaction is required. In either case, there is a one-processor-cycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automatically incremented, and another access can occur. Through the IDMAA register, the processor can also specify the starting address and data format for DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-21MOD980N to write the address onto the IAD [14:0] bus into the IDMA Control Register. If IAD [15] is set to 0, IDMA latches the address. If IAD [15] is set to 1, IDMA latches OVLAY memory. The IDMAA register is memory mapped at address DM (0x3FE0). Note that the latched address (IDMAA) or overlay register cannot be read back by the host. The IDMA OVERLAY register is memory mapped at address DM(0x3FE7). See Figure on page 13 for more information on IDMA memory mapping. When bit 14 in 0x3FE7 is set to 1, then timing in Figure on page 35 applies for short reads. When bit 14 in 0x3FE7 is set to zero short reads use the timing shown in Figure on page 34.
The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written to, while the ADSP-21MOD980N is operating at full speed. The processor memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address
IDM A O V ER LA Y 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
DM (0x3FE7)
RESE RVE D SET TO 0 RESE RVE D ALW A YS SET TO 0 Short R ead O nly En able 1 = Enable 0 = D isable
ID DM O VLAY
ID PM O VLAY
IDM A CO NTR O L (U=U ND EF IN ED AT R ESE T) 15 0 14 U 13 U 12 U 11 U 10 U 9 U 8 U 7 U 6 U 5 U 4 U 3 U 2 U 1 U 0 U
DM (0x3FE0)
RESE RVE D ALW A YS SET TO 0
IDM AD Destination m em ory type: 0=PM 1=DM
IDM AA ADDR ESS
Figure 9. IDMA Control/OVLAY Registers
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PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
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A LW A Y S A C CE S S IB LE A T A D DR E S S 0x0000 - 0x 1F F F
A LW A Y S A C CE S S IB LE A T A D DR E S S 0x2000 - 0x 3F F F
0x20 00 - 0x 3F F F 0x2000 - 0x 3F F F A C CE S S IB LE W H E N P M O V LA Y = 0 A C CE S S IB LE W H E N P M O V LA Y = 4 A C CE S S IB LE W H E N P M O V LA Y = 5 A C CE S S IB LE W H E N P M O V LA Y = 6 A C CE S S IB LE W H E N P M O V LA Y = 7 0x2000 - 0x 3F F F 0x2000 - 0x 3F F F 0x2000 - 0x 3F F F A C CE S S IB LE W H E N DM O V LA Y = 0 A C CE S S IB LE W H E N DM O V LA Y = 4
0x0000 - 0x 1F F F 0x0000 - 0x 1F F F 0x0000 - 0x 1F F F 0x00 00 - 0x 1F F F 0x0000 - 0x 1F F F
A C CE S S IB LE W H E N DM O V LA Y = 5 A C CE S S IB LE W H E N DM O V LA Y = 6 A C CE S S IB LE W H E N DM O V LA Y = 7 A C CE S S IB LE W H E N DM O V LA Y = 8
0x0000 - 0x 1F F F
Figure 10. Direct Memory Access - PM and DM Memory Maps
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ADSP-21MOD980N
IDMA PORT BOOTING
The ADSP-21MOD980N boots programs through its Internal DMA port.When Mode C = 1, Mode B = 0, and Mode A = 1, the ADSP-21MOD980N boots from the IDMA port. IDMA feature can load as much on-chip memory as desired. Program execution is held off until on-chip program memory location 0 is written to.
FLAG I/O PINS
Each modem processor has eight general purpose programmable input/output flag pins. They are controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-21MOD980N's clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during RESET. Note: Pins PF0, PF1, and PF2 are also used for device configuration during RESET. Since they are multiplexed within the ADSP-21MOD980N, PF[2:0] should be configured as an output for only one processor at a time.
REV. PrB 6/2001
15
PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
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DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-21MOD980N has on-chip emulation support and an ICE-Port, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE's in-circuit probe, a 14-pin plug.
The EZ-ICE can emulate only one modem processor at a time. You must include hardware to select which processor in the ADSP-21MOD980N you want to emulate. Figure on page 16 is a functional representation of the modem processor selection hardware. You can use one ICE-Port connector with two ADSP-21MOD980N processors without using additional buffers.
A D S P-2 1 M O D 9 8 0 N ELOUT E BR E BG E INT E L IN E CL K EMS E RE S E T
G ND 1 E BG 3 E BR 5 KE Y 7 ELOUT 9 EE 11 RE S E T 13 14 12 10 8 6 4 2
BG
BR
BG 0 BR 0 RE S E T 0 EE0 BG 1 BR 1 RE S E T 1 EE1 BG 2 BR 2 RE S E T 2 EE2 BG 3 BR 3 RE S E T 3 EE3 BG 4 BR 4 RE S E T 4 EE4 BG 5 BR 5 RE S E T 5 EE5
E NT
E L IN
E CL K
EMS
E RE S E T
BG 6 BR 6 RE S E T 6 EE6
BG 7 BR 7 RE S E T 7 EE7
Figure 11. Selecting a Modem Processor in the ADSP-21MOD980N
Issuing the "chip reset" command during emulation causes the modem processor to perform a full chip reset, including a reset of its memory mode. Therefore, it is vital that the 16
mode pins are set correctly PRIOR to issuing a chip reset command from the emulator user interface. As the mode pins share functionality with PF[2:0] on the 6/2001 REV. PrB
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ADSP-21MOD980N
ADSP-21MOD980N, it may be necessary to reset the target hardware separately to insure the proper mode selection state on emulator chip reset. See the ADSP-2100 Family EZ-Tools data sheet for complete information on ICE products. The ICE-Port interface consists of the following ADSP-21MOD980N pins: EBR EINT EE EBG ECLK ERESET ELIN EMS ELOUT These ADSP-21MOD980N pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors. The traces for these signals between the ADSP-21MOD980N and the connector must be kept as short as possible--no longer than 3 inches. The following pins are also used by the EZ-ICE: * * * * BR BG RESET GND
Pin spacing should be 0.1 0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ-ICE probe plug.
1 GND
2
BG
EBG EBR
KEY (N O PIN)
3
4
BR
5
6
EINT
7
8
ELIN
10
9
ELOUT
11 12
ECLK EMS
13 14
EE
RESET
ERESET
TO P VIEW
Figure 12. Target Board Connector for EZ-ICE
Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec.
TARGET MEMORY INTERFACE
For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed below.
TARGET SYSTEM INTERFACE SIGNALS
The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-21MOD980N in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. The EZ-ICE connects to your target system via a ribbon cable and a 14-pin female plug. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board.
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
When the EZ-ICE board is installed, the performance on some system signals change. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE board: * EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the processor on the RESET signal. EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the processor on the BR signal. EZ-ICE emulation ignores RESET and BR when single-stepping. EZ-ICE emulation ignores RESET and BR when in Emulator Space (processor halted). EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the processor's external memory bus only if bus grant (BG) is asserted by the EZ-ICE board's processor.
*
* * *
The EZ-ICE connector (a standard pin strip header) is shown in Figure on page 17. You must add this connector to your target board design if you intend to use the EZ-ICE. Be sure to allow enough room in your system to fit the EZ-ICE probe onto the 14-pin connector. The 14-pin, 2-row pin strip header is keyed at the Pin 7 location--you must remove Pin 7 from the header. The pins must be 0.025 inch square and at least 0.20 inch in length.
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PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
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ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Description Min Max Unit
VDDEXT VDDINT VINPUT TAMB
External supply Internal supply Input Voltage Ambient temperature
2.98 1.81 VIL= -0.3 0
3.63 2.0 VIH= +3.6 +70
V V V C
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Min Typ Max Unit
VIH, Hi-Level Input Voltage1, 2 VIH, Hi-Level CLKIN Voltage VIL, Lo-Level Input Voltage1, 3 VOH, Hi-Level Output Voltage1, 4, 5
@ VDDINT = max @ VDDINT = max @ VDDINT = min @ VDDEXT = min IOH = -0.5 mA @ VDDEXT = min IOH = -100 A6
1.5 2.0 0.7 2.4 VDDEXT -0.3 0.4 10 10 10 10
V V V V V V A A A A
VOL, Lo-Level Output Voltage1, 4, 5 IIH, Hi-Level Input Leakage Current3 IIL, Lo-Level Input Leakage Current3 IOZH, Three-State Leakage Current7 IOZL, Three-State Leakage Current7
@ VDDEXT = min IOL = 2 mA @ VDDINT = max VIN = 3.6V @ VDDINT = max VIN = 0 V @ VDDEXT = max VIN = 3.6V8 @ VDDEXT = max VIN = 0 V8
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ADSP-21MOD980N
Typ Max Unit
ELECTRICAL CHARACTERISTICS (CONTINUED)
Parameter Test Conditions Min
IDD, Supply Current (Idle) IDD, Supply Current (Dynamic)
@ VDDINT = 1.9V tCK = 12.5 ns @ VDDINT = 1.9V tCK = 12.5 ns9 TAMB = +25C Lowest power mode @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25C @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25C @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25C @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB= +25C @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB= +25C @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB= +25C
50 200
mA mA
IDD, Supply Current (Powerdown)10 CI, Input Pin Capacitance
RESET, BR, IS, TFS0, PF[7:4]
800 8 32 64 8 32 64
A pF pF pF pF pF pF
CI, Input Pin Capacitance
IWR, IRD, IAL, DR0, RFS0, SCLK0, IAD [15:0]
CI, Input Pin Capacitance
TFS1, PF[2:0], CLKIN, DR1, RFS1, SCLK1
CO, Output Pin Capacitance1, 6, 7, 10, 11
BG, CLKOUT, TFS0, PF[7:4], DT1
CO, Output Pin Capacitance1, 6, 7, 9, 10
IAD [15:0], DT0, IACK, RFS0, SCLK0
CO, Output Pin Capacitance1, 6, 7, 9, 10
SCLK1, TFS1, PF[2:0], DATA [23:8], A0, RFS1
1 2 3 4 5
Bidirectional pins: RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD [15:0], PF[2:0], PF[7:4]. Input only pins: RESET, BR, DR0, DR1, IS, IAL,IRD, IWR. Input only pins: CLKIN, RESET, BR, DR0, DR1. Output pins: BG, A0, DT0, DT1, CLKOUT, IACK. Although specified for TTL outputs, all ADSP-21MOD980N outputs are CMOS-compatible and will drive to VDDEXT and GND, assuming no DC loads. Guaranteed but not tested. Three-statable pins: DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, IAD[15:0]. 0 Volts on BR. Vin = 0V and 3V. For typical supply current figures refer to "Power Dissipation" section. See the ADSP-2100 Family User's Manual for details. Output pin capacitance is the capacitive load for any three-stated output pin
6 7 8 9 10 11
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PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
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ABSOLUTE MAXIMUM RATINGS
Parameter Description Min. Max Unit
VDDINT VDDEXT
Internal Supply Voltage External Supply Voltage Input Voltage1 Output Voltage Swing2 Storage Temperature Range
-0.3 -0.3 -0.5 -0.5 -65 C
+2.5 +4.6 +4.6 VDDEXT + 0.5 +150 C
V V V V C
1
Applies to bidirectional pins (D0:D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1:A13, PF0:PF7) and input only pins (CLKIN, RESET, BR, DR0, DR1). Applies to output pins (BG, PWDACK, A0, DT0, DT1, CLKOUT).
2
ESD SENSITIVITY
CAUTION: ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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ADSP-21MOD980N
POWER DISSIPATION
To determine total power dissipation in a specific application, the following equation should be applied for each output: C VDD2 f C = load capacitance f = output switching frequency Example: In an application where an external host is accessing internal memory and no other outputs are active, power dissipation is calculated as follows:
Table 7. Example Power Dissipation Calculation Parameters # of Pins x C (pF)
Assumptions: Assumptions: * * * * External data memory is accessed every fourth cycle with 50% of the address pins switching. External data memory writes occur every fourth cycle with 50% of the data pins switching. Each address and data pin has a 64 pF total load at the pin. Application operates at VDDEXT = 3.3 V and tCK = 30 ns. VDDEXT2 f)
Total Power Dissipation = PINT + (C
P INT= internal power dissipation from Figure 15 VDDEXT2 f) is calculated for each output, as in the (C example in Table 7.
x VDDEXT2 (V)
x f (MHz)
PD (mW)
Address Data Output, WR
8 9
64 64
3.32 3.32
18.8 18.8
104.8 117.9 222.7
Total power dissipation for this example is: PD = PINT + 222.7 mW
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PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
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ENVIRONMENTAL CONDITIONS
M O D 9 80 N C o r e P O W E R , ID L E
12 0
Table 8. Thermal Resistance
108m W
11 0
10 0
V D D = 2 .0 v
90
96m W
Rating Description1
Symbol
PBGA
84m W
80
V D D = 1 .9 v V D D = 1 .8 v
84m W
76m W
70
68m W
Thermal Resistance (Case-toAmbient) Thermal Resistance (Junction-toAmbient) Thermal Resistance (Junction-toCase)
1
CA
23C /W 28.2C /W 5.2C /W
60
JA
50 55 60 65 70 75 80 85
1/t C K - M H z
JC
M O D 9 8 0N C o r e P O W E R , D Y N A M I C
47 5
440m W
42 5
37 5
V D D = 2 .0 V
375m W
Where the Ambient Temperature Rating (TAMB) is: TAMB = TCASE - (PD x CA) TCASE = Case Temperature in C PD = Power Dissipation in W
336m W
32 5
336m W
V D D = 1 .9 V
27 5
287m W 256m W
V D D = 1 .8 V
22 5
17 5 55 60 65 70 75 80 85
1/tC K - M H z
Figure 13. Power vs. Frequency
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ADSP-21MOD980N
TEST CONDITIONS
Output Disable Time
IN PU T
1.5V
O UT P UT
2.0V 1.5V 0.8V
Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference of tMEASURED and tDECAY, as shown in Figure 16. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. The decay time, tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation:
C L x 0.5V t DECAY = ------------------------iL
Figure 14. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
IO L
from which
t DIS = tMEASURED - tDECAY
TO O UT P UT P IN 50p F 1.5V
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving.
Output Enable Time
IO H
Figure 15. Equivalent Loading for AC Measurements (Including All Fixtures)
RE F E RE NC E S IG N AL
t M E A S UR E D tE N A
VOH (M E A SU R E D) V O H (M E A SU RE D ) - 0.5V O UT P UT V O L (M E A SU RE D ) +0.5V V OL (M E A SU R E D) 1.0V V OL (M E A SU R E D) O UT P UT S TA RT S DR IV ING 2.0V
t DIS
Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in Figure 16. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
V OH (M E A SU R E D)
t DE CA Y
O UT P UT S TO P S DR IV ING
HIG H-IM P E DAN CE S T AT E . T ES T CO ND IT IO N S CAU S E T HIS V O LT AGE L EV E L T O B E AP P RO XIM AT E LY 1.5V.
Figure 16. Output Enable/Disable
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PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
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TIMING SPECIFICATIONS
RIS E TIM E (0.4V - 2.4V ) - ns
30 T = 85 C V D D = 0V T O 2.0V 25
This section contains timing information for the DSP's external signals.
General Notes
20
15
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive longer times.
Timing Notes
10
5
0 0 50 100 150 CL - pF 200 250 300
V AL ID O UTP UT D EL AY O R H O LD - n s
Switching characteristics specify how the processor changes its signals. You have no control over this timing--circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.
Frequency Dependency For Timing Specifications
Figure 17. Typical Output Rise Time vs.Load Capacitance (at Maximum Ambient Operating Temperature)
18 16 14 12 10 8 6 4 2 N OM IN AL -2 -4 -6 0 50 100 CL - pF 150 200 250
tCK is defined as 0.5 tCKI. The ADSP-21MOD980N uses an input clock with a frequency equal to half the instruction rate. For example, a 40 MHz input clock (which is equivalent to 25 ns) yields a 12.5 ns processor cycle (equivalent to 80 MHz). tCK values within the range of 0.5 tCKI period should be substituted for all relevant timing parameters to obtain the specification value. Example: tCKH = 0.5 tCK - 2 ns = 0.5 (12.5 ns) - 2 ns = 4.25 ns
Output Drive Currents
Figure 18. Typical Output Valid Delay or Hold vs.Load Capacitance, CL (at Maximum Ambient Operating Temperature)
Figure 14 shows typical I-V characteristics for the output drivers on the ADSP-21MOD980N. The curves represent the current drive capability of the output drivers as a function of output voltage
Capacitive Loading
Figure 16 and Figure 17 show the capacitive loading characteristics of the ADSP-21MOD980N.
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ADSP-21MOD980N
Clock and Reset Signals Table 9. Clock and Reset Signals Parameter Description Min. Max Unit
Clock signals (Timing Requirements): tCKI tCKIL tCKIH tCKRISE tCKFALL CLKIN Period CLKIN Width Low CLKIN Width High CLKIN rise time1 CLKIN fall time 25.0 8 8 4 4 40.0 ns ns ns ns ns
Clock signals (Switching Characteristics)2: tCKL tCKH tCKOH CLKOUT Width Low CLKOUT Width High CLKIN High to CLKOUT High 0.5tCK - 3 0.5tCK - 3 0 8 ns ns ns
Control Signals (Timing Requirements): tRSP tMS tMH
1 2 3
RESET Width Low Mode Setup Before RESET High Mode Hold After RESET High
5tCK3 4 5
ns ns ns
tCKRISE and tCKFALL are specified between the 10% and 90% points on the signal edge. If it is not needed by the application, CLKOUT should be disabled to reduce noise (DM(0x3FF3) bit 14). Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time).
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PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
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tCK I tC KI H
CL K IN
tC K I L tCK O H tC KH
CL K O U T
tC K L
PF (2 :0 )*
tMS
RE S E T
tM H
*PF 2 is M o d e C , PF 1 i s M o d e B , PF 0 is M o d e A
Figure 19. Clock and Reset Signals
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ADSP-21MOD980N
Interrupts and Flags Table 10. Interrupts and Flags Parameter Description Min. Max Unit
Timing Requirements: tIFS tIFH IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 0.25tCK + 10 0.25tCK ns ns
Switching Characteristics: tFOH tFOD
1
Flag Output Hold after CLKOUT Low5 Flag Output Delay from CLKOUT Low5
0.5tCK - 5 0.5tCK + 4
ns ns
If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User's Manual for further information on interrupt servicing.) Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced. IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE. PFx = PF0, PF1, PF2, PF4, PF5, PF6, PF7. Flag Outputs = PFx, Flag_out4.
2 3 4 5
CLKOU T
tIF H
IR Q x FI PF x
t IF S
Figure 20. Interrupts and Flags
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PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
Serial Ports Table 11. Serial Ports Parameter Description Min. Max Unit
For current information contact Analog Devices at (800) ANALOGD
Timing Requirements: tSCK tSCS tSCH tSCP SCLK Period DR/TFS/RFS Setup before SCLK Low DR/TFS/RFS Hold after SCLK Low SCLKIN Width 30 4 7 12 ns ns ns ns
Switching Characteristics: tCC tSCDE tSCDV tRH tRD tSCDH tTDE tTDV tSCDD tRDV CLKOUT High to SCLKOUT SCLK High to DT Enable SCLK High to DT Valid TFS/RFSOUT Hold after SCLK High TFS/RFSOUT Delay from SCLK High DT Hold after SCLK High TFS (Alt) to DT Enable TFS (Alt) to DT Valid SCLK High to DT Disable RFS (Multichannel, Frame Delay Zero to DT Valid 0 0 12 12 12 0 12 0.25tCK 0 12 0.25tCK + 6 ns ns ns ns ns ns ns ns ns ns
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ADSP-21MOD980N
CL K O U T
tC C
tC C
tS CK
S CL K
tS C P tS C S tS CH tS C P
DR TF S IN RFS IN
tR D tR H
RFS O U T TFS OU T
tS CD D tS C D V tS C DE tS CD H
DT
tT DE tT D V
TFSOU T
ALTERN ATE FR A M E M O D E
tR DV
RF S O UT
M U L T IC H A N N E L MODE, FRAM E DE LAY 0 (M F D = 0 )
tT D E tT D V
T F S IN
ALTERN ATE FR A M E M O D E
tR DV
RF S IN
M U L T IC H A N N E L MODE, FRAM E DE LAY 0 (M F D = 0 )
Figure 21. Serial Ports
REV. PrB 6/2001
29
PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
IDMA Address Latch Table 12. IDMA Address Latch Parameter Description Min. Max Unit
For current information contact Analog Devices at (800) ANALOGD
Timing Requirements: tIALP tIASU tIAH tIKA tIALS tIALD
1 2 3 4
Duration of Address Latch1, 2, 3 IAD[15:0] Address Setup before Address Latch End2, 3 IAD[15:0] Address Hold after Address Latch End2, 3 IACK Low before Start of Address Latch2, 3, 4 Start of Write or Read after Address Latch End2, 3, 4 Address Latch Start after Address Latch End1, 2, 3
10 5 3 0 3 2
ns ns ns ns ns ns
Start of Address Latch = IS Low and IAL High. End of Address Latch = IS High or IAL Low. For IDMA, please refer to the ADSP-2100 Family User's Manual. Start of Write or Read = IS Low and IWR Low or IRD Low.
IA C K
t IK A
IA L
tIA L D
t IA L P
IS
t IA L P
IA D 1 5 -0
t IA S U
t IA H
tIA S U
t IA H t IA L S
IRD O R IWR
Figure 22. IDMA Address Latch
30
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21MOD980N
IDMA Write, Short Write Cycle Table 13. IDMA Write, Short Write Cycle Parameter Description Min. Max Unit
Timing Requirements: tIKW tIWP tIDSU tIDH IACK Low before Start of Write1, 2 Duration of Write1, 2, 3 IAD[15:0] Data Setup before End of Write2, 3, 4, 5 IAD[15:0] Data Hold after End of Write2, 3, 4, 5 0 10 3 2 ns ns ns ns
Switching Characteristics: tIKHW
1 2 3 4 5
Start of Write to IACK High
10
ns
Start of Write = IS Low and IWR Low. For IDMA, please refer to the ADSP-2100 Family User's Manual. End of Write = IS High or IWR High. If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH. If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.
t IK W
IA C K
t IK H W
IS
t IW P
IW R
t ID H t ID SU
IA D 15-0 DA T A
Figure 23. IDMA Write, Short Write Cycle
REV. PrB 6/2001
31
PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
IDMA Write, Long Write Cycle Table 14. IDMA Write, Long Write Cycle Parameter Description Min. Max Unit
For current information contact Analog Devices at (800) ANALOGD
Timing Requirements tIKW tIKSU tIKH IACK Low before Start of Write1 IAD[15:0] Data Setup before End of Write2, 3, 4 IAD[15:0] Data Hold after End of Write2, 3, 4 0 0.5tCK + 5 0 ns ns ns
Switching Characteristics: tIKLW tIKHW
1 2 3 4
Start of Write to IACK Low4 Start of Write to IACK High
1.5tCK 10
ns ns
Start of Write = IS Low and IWR Low. If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH. If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH. This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User's Manual.
t IK W
IA C K
t IK H W t IK LW
IS
IW R
t IK S U
t IK H
DA T A
IAD 15-0
Figure 24. IDMA Write, Long Write Cycle
32
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21MOD980N
IDMA Read, Long Read Cycle Table 15. IDMA Read, Long Read Cycle Parameter Description Min. Max Unit
Timing Requirements: tIKR tIRK IACK Low before Start of Read1, 2 End of Read after IACK Low2, 3 0 2 ns ns
Switching Characteristics: tIKHR tIKDS tIKDH tIKDD tIRDE tIRDV tIRDH1 tIRDH2
1 2 3 4 5
IACK High after Start of Read1, 2 IAD[15:0 Data Setup before IACK Low2 IAD[15:0] Data Hold after End of Read2, 3 IAD[15:0] Data Disabled after End of Read2, 3 IAD[15:0] Previous Data Enabled after Start of Read2 IAD[15:0] Previous Data Valid after Start of Read2 IAD[15:0] Previous Data Hold after Start of Read (DM/PM1)2, 4 IAD[15:0] Previous Data Hold after Start of Read (PM2)2, 5 2tCK - 5 tCK - 5 0 0.5tCK - 2 0
10
ns ns ns
10
ns ns
10
ns ns ns
Start of Read = IS Low and IRD Low. For IDMA, please refer to the ADSP-2100 Family User's Manual. End of Read = IS High or IRD High. DM read or first half of PM read. Second half of PM read.
IA C K
t IK H R t IK R
IS
t IR K
IR D
t IR D E
P RE V IO US DA T A
t IK D S
RE A D DA T A
t IK D H
IA D 15-0
t IR D V t IR D H
t IK D D
Figure 25. IDMA Read, Long Read Cycle
REV. PrB 6/2001
33
PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
IDMA Read, Short Read Cycle Table 16. IDMA Read, Short Read Cycle1 Parameter Description Min. Max Unit
For current information contact Analog Devices at (800) ANALOGD
Timing Requirements: tIKR tIRP IACK Low before Start of Read2 Duration of Read 0 10 ns ns
Switching Characteristics: tIKHR tIKDH tIKDD tIRDE tIRDV tIRDH1 tIRDH2
1 2 3 4 5 6
IACK High after Start of Read2, 3 IAD[15:0] Data Hold after End of Read3, 4 IAD[15:0] Data Disabled after End of Read3, 4 IAD[15:0] Previous Data Enabled after Start of Read3 IAD[15:0] Previous Data Valid after Start of Read3 IAD[15:0] Previous Data Hold after Start of Read (DM/PM1)3,5 IAD[15:0] Previous Data Hold after Start of Read (PM2)3, 6 2tCK - 5 tCK - 5 0 0
10
ns ns
10
ns ns
10
ns ns ns
Timing applies to ADSP-21MOD980N when Short Read Only mode is disabled. See Table on page 35. Start of Read = IS Low and IRD Low. For IDMA, please refer to the ADSP-2100 Family User's Manual. End of Read = IS High or IRD High. DM read or first half of PM read. Second half of PM read.
IACK
tIKR
IS
tIKHR
IR D
tIRDE IAD[15:0] tIRDV Previous Data New Read Data
Figure 26. IDMA Read, Short Read Cycle
34
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21MOD980N
IDMA Read - Short Read Cycle in Short Read Only Mode Table 17. IDMA Read - Short Read Cycle in Short Read Only Mode1 Parameter Description Min. Max Unit
Timing Requirements: tIKR tIRP IACK Low before Start of Read2, 4 Duration of Read after IACK Low3, 4 0 10 ns ns
Switching Characteristics: tIKHR tIKDH tIKDD tIRDE tIRDV
1
IACK High after Start of Read2, 4 IAD[15:0] Previous Data Hold after End of Read3, 4 IAD[15:0] Previous Data Disabled after End of Read3, 4 IAD[15:0] Previous Data Enabled after Start of Read4 IAD[15:0] Previous Data Valid after Start of Read4 0 0
10
ns ns
10
ns ns
10
ns
Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register or by an external host writing to the register. Disabled by default. Start of Read = IS Low and IRD Low. Previous data remains until end of read. End of Read = IS High or IRD High. For IDMA, please refer to the ADSP-2100 Family User's Manual.
2 3 4
IACK
tIKR
IS
tIKHR
IR D
tIRDE
tIKDH
IAD[15:0]
Previous Data tRDV tIKDD
Figure 27. IDMA Read, Short Read Only Mode
REV. PrB 6/2001
35
PRELIMINARY TECHNICAL DATA ADSP-21MOD980N 352-BALL PBGA PACKAGE PINOUT
A physical layout of all signals is shown in the following tables. Figure on page 40 shows the signals on the left side of the device when viewed from the top. Figure on page 41 shows the signals on the right side of the device when viewed from the top. The pin number for each signal is listed in Table on page 36.
Table 18. Pinout by Signal Name
For current information contact Analog Devices at (800) ANALOGD
Table 18. Pinout by Signal Name (Continued)
Table 18. Pinout by Signal Name (Continued)
Table 18. Pinout by Signal Name (Continued)
Signal Name CLKOUT_3 CLKOUT_4 CLKOUT_5 CLKOUT_6 CLKOUT_7 CLKOUT_8 D08 D09 D10 D11
Pin C20 AC1 L24 P4 AD10 AF15 F23 E25 E24 D26 D25 D24 C26 C25 B26 B24 A25 B23 C23 A24 A23 A22 E1 AF22 AE7 P2 AF20 P3 A12 D21
Signal Name DT1_4 DT1_5 DT1_6 DT1_7 DT1_8 EBG EBR ECLK EE_1 EE_2 EE_3 EE_4 EE_5 EE_6 EE_7 EE_8 EINT ELIN ELOUT EMS ERESET GND GND GND GND GND GND GND GND GND
Pin AF2 T25 U3 AD13 AE20 F26 G26 J23 M4 C13 G23 AE9 T26 Y2 AC13 AE22 J26 J25 J24 E23 E26 D19 D20 D23 F1 F2 F4 G2 G3 H1
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Pin H2 H3 H4 H23 H24 H25 H26 N1 N2 N3 N4 R23 R24 T3 T24 U1 U2 U23 U24 U25 U26 W1 W2 W3 W4 AF1 AF4 AF8 AF10 AF12
Signal Name A0 BG_1 BG_2 BG_3 BG_4 BG_5 BG_6 BG_7 BG_8 BR_1 BR_2 BR_3 BR_4 BR_5 BR_6 BR_7 BR_8 CLKIN CLKOUT_1 CLKOUT_2 36
Pin D12 A2 F3 D14 F25 AC5 R25 R4 AD15 AD25 G4 B13 G25 AC9 N24 U4 AE15 AE26 E3 G1 A10 6/2001 REV. PrB D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 DR0A DR0B DR1 DT0A DT0B DT1_1 DT1_2 DT1_3
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21MOD980N
Table 18. Pinout by Signal Name (Continued)
Table 18. Pinout by Signal Name (Continued)
Table 18. Pinout by Signal Name (Continued)
Table 18. Pinout by Signal Name (Continued)
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Pin AF16 AF17 AF21 AF23 AF26 B2 B5 B11 B12 B16 B19 B21 B25 C3 C5 C11 C16 C19 C21 C24 D4 D5 D11 D16 AC12 AC17 AC21 AC23 AD2 AD3
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Pin AD4 AD5 AD7 AD8 AD11 AD12 AD16 AD17 AD21 AD22 AD23 AD24 AE1 AE2 AE4 AE8 AE10 AE12 AE16 AE17 AE21 AE23 AE25 A1 A5 A11 A16 A19 A20 A21
Signal Name GND GND GND GND GND GND GND GND GND GND IACK_A IACK_B IAD0_A IAD0_B IAD1_A IAD1_B IAD10_A IAD10_B IAD11_A IAD11_B IAD12_A IAD12_B IAD13_A IAD13_B IAD14_A IAD14_B IAD15_A IAD15_B IAD2_A IAD2_B
Pin A26 AA23 AA24 AA25 AA26 AC4 AC6 AC8 AC10 W23 T4 AC26 B4 V26 B1 V23 AA2 L26 V3 L23 AA4 M25 E2 AD26 D1 AC24 E4 AC25 C2 V24
Signal Name IAD3_A IAD3_B IAD4_A IAD4_B IAD5_A IAD5_B IAD6_A IAD6_B IAD7_A IAD7_B IAD8_A IAD8_B IAD9_A IAD9_B IAL_A IAL_B IRD_A IRD_B IS_1 IS_2 IS_3 IS_4 IS_5 IS_6 IS_7 IS_8 IWR_A IWR_B PF0 PF1
Pin D3 W24 C1 W25 D2 W26 V4 M26 Y4 N26 AD6 M23 Y3 M24 C8 Y25 C4 Y24 D6 A14 F24 AA3 V25 AC7 AC16 Y26 D8 Y23 A6 B6
REV. PrB 6/2001
37
PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
Table 18. Pinout by Signal Name (Continued)
For current information contact Analog Devices at (800) ANALOGD
Table 18. Pinout by Signal Name (Continued)
Table 18. Pinout by Signal Name (Continued)
Table 18. Pinout by Signal Name (Continued)
Signal Name PF2 PF4_1 PF4_2 PF4_3 PF4_4 PF4_5 PF4_6 PF4_7 PF4_8 PF5_1 PF5_2 PF5_3 PF5_4 PF5_5 PF5_6 PF5_7 PF5-8 PF6_1 PF6_2 PF6_3 PF6_4 PF6_5 PF6_6 PF6_7 PF6_8 PF7_1 PF7_2 PF7_3 PF7_4 PF7_5
Pin C6 M1 C10 D18 AC2 L25 T1 AF7 AD18 M2 D10 C18 AC3 G24 V1 AE11 AE18 M3 B10 B18 AD1 R26 T2 AD9 AC18 J4 D12 A18 AE3 N25
Signal Name PF7_6 PF7_7 PF7_8 RESET_1 RESET_2 RESET_3 RESET_4 RESET_5 RESET_6 RESET_7 RESET_8 RFS0A RFS0B RFS1 SCLK0A SCLK0B SCLK1 TFS0_1 TFS0_2 TFS0_3 TFS0_4 TFS0_5 TFS0_6 TFS0_7 TFS0_8 TFS1 VDDEXT VDDEXT VDDEXT VDDEXT
Pin V2 AF9 AF18 J1 D13 C22 AF6 T23 AA1 AC11 AC22 J3 AD20 AE6 P1 AE24 AF5 J2 C12 B20 AE5 N23 Y1 AF11 AC20 AF3 B22 C7 C9 C14
Signal Name VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT
Pin C15 C17 D7 D9 D15 D17 D22 K1 K2 K3 K4 K23 K24 K25 K26 L1 L2 L3 L4 A7 A8 A9 A13 A15 A17 AC14 AC15 AC19 AD14 AD19
Signal Name VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT
Pin AE14 AE19 AF14 AF19 B7 B8 B9 B14 B15 B17 A3 A4 AB1 AB2 AB3 AB4 AB23 AB24 AB25 AB26 AE13 AF13 AF24 AF25 B3 P23 P24 P25 P26
38
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21MOD980N
Table 18. Pinout by Signal Name (Continued)
Signal Name VDDINT VDDINT VDDINT
Pin R1 R2 R3
REV. PrB 6/2001
39
PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
For current information contact Analog Devices at (800) ANALOGD
Signals by Pin Location--Top View, Left to Right
1 2 3 4 5 6 7 8 9 10 11 12 13
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
GND IAD1_A IAD4_A IAD14_A DR0A GND CLKOUT_1 GND RESET_1 VDDEXT VDDEXT PF4_1 GND SCLK0A VDDINT PF4_6 GND PF5_6 GND TFS0_6 RESET_6 VDDINT CLKOUT_4 PF6_4 GND GND
A0 GND IAD2_A IAD6_A IAD13_A GND GND GND TFS0_1 VDDEXT VDDEXT PF5_1 GND DT0A VDDINT PF6_6 GND PF7_6 GND EE_6 IAD10_A VDDINT PF4_4 GND GND DT1_4
VDDINT VDDINT GND IAD3_A CLKIN BG_1 GND GND RFS0A VDDEXT VDDEXT PF6_1 GND DT1_1 VDDINT GND DT1_6 IAD11_A GND IAD9_A IS_4 VDDINT PF5_4 GND PF7_4 TFS1
VDDINT IAD0_A IRD_A GND IAD15_A GND BR_1 GND PF7_1 VDDEXT VDDEXT EE_1 GND CLKOUT_6 BG_6 IACK_A BR_6 IAD6_A GND IAD7_A IAD12_A VDDINT GND GND GND GND
GND GND GND GND
PF0 PF1 PF2 IS_1
VDDEXT VDDEXT VDDEXT VDDEXT
VDDEXT VDDEXT IAL_A IWR_A
VDDEXT VDDEXT VDDEXT VDDEXT
CLKOUT_2 PF6_2 PF4_2 PF5_2
GND GND GND GND
DT1_2 GND TFS0_2 PF7_2
VDDEXT BR_2 EE_2 RESET_2
BG_4 GND TFS0_4 SCLK1
GND IAD8_A RFS1 RESET_4
IS_6 GND DR1 PF4_7
GND GND GND GND
BR_4 PF6_7 EE_4 PF7_7
GND CLKOUT_7 GND GND
RESET_7 GND PF5_7 TFS0_7
GND GND GND GND
EE_7 DT1_7 VDDINT VDDINT
1
2
3
4
5
6
7
8
9
10
11
12
13
40
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21MOD980N
OUTLINE DIMENSIONS - 352 PLASTIC BALL GRID ARRAY
Signals by Pin Location--Top View, Left to Right (Continued)
14 15 16 17 18 19 20 21 22 23 24 25 26
IS_2 VDDEXT VDDEXT BG_2
VDDEXT VDDEXT VDDEXT VDDEXT
GND GND GND GND
VDDEXT VDDEXT VDDEXT VDDEXT
PF7_3 PF6_3 PF5_3 PF4_3
GND GND GND GND
GND TRS0_3 CLKOUT_3 GND
GND GND GND DT1_3
D23 VDDEXT RESET_3 VDDEXT
D22 D19 D20 GND EMS D08 EE_3 GND ECLK VDDEXT IAD11_B IAD8_B TFS0_5 VDDINT GND RESET_5 GND IAD1_B GND IWR_B GND VDDINT
D21 D17 GND D13 D10 IS_3 PF5_5 GND ELOUT VDDEXT CLKOUT_5 IAD9_B BR_5 VDDINT GND GND GND IAD2_B IAD3_B IRD_B GND VDDINT IAD14_B GND SCLK0B VDDINT
D18 GND D15 D12 D09 BG_3 BR_3 GND ELIN VDDEXT PF4_5 IAD12_B PF7_5 VDDINT BG_5 DT1_5 GND IS_5 IAD4_B IAL_B GND VDDINT IAD15_B BG_8 GND VDDINT
GND D16 D14 D11 ERESET EBG EBR GND EINT VDDEXT IAD10_B IAD6_B IAD7_B VDDINT PF6_5 EE_5 GND IAD0_B IAD5_B IS_8 GND VDDINT IACK_B IAD13_B BR_8 GND
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
VDDEXT VDDEXT VDDEXT VDDEXT
VDDEXT BG_7 BR_7 CLKOUT_8
IS_7 GND GND GND
GND GND GND GND
PF6_8 PF4_8 PF5_8 PF7_8
VDDEXT VDDEXT VDDEXT VDDEXT
TFS0_8 RFS0B DT1_8 DT0B
GND GND GND GND
RESET_8 GND EE_8 DR0B
GND GND GND GND
14
15
16
17
18
19
20
21
22
23
24
25
26
REV. PrB 6/2001
41
PRELIMINARY TECHNICAL DATA ADSP-21MOD980N
BA L L A1 IN DIC AT O R
For current information contact Analog Devices at (800) ANALOGD
35.00 BS C S Q
26 25
24 23
22 21
20 19
18 17
16 15
14 13
12 11
10 9
8 7
6 5
4 3
2 1 A B C D E F G H J K L M
T O P V IE W
BO T T O M V IE W
N P R T U V W Y AA AB AC AD AE AF
30.70 30.00 S Q 29.50 DE T A IL A 2.62 2.37 2.12
1.27 B SC S Q BA L L PITC H 31.75 BS C S Q 1.22 1.17 1.12
0.70 0.60 0.50 0.70 0.60 0.50 0.90 0.75 0.60 BA L L DIA M E T E R
NO T E S : 1. T HE AC T UA L P O S IT IO N O F T HE B AL L G R ID IS W IT HIN 0.30 O F T HE IDE A L P O S IT IO N R EL A TIVE T O TH E P AC KAG E E DG E S . 2. T HE AC T UA L P O S IT IO N O F EA CH BA L L IS W IT HIN 0.15 O F ITS ID E AL PO SITIO N RE L AT IV E T O THE B AL L G RID . 3. CE N T ER F IG U RE S A RE N O M INA L UN LE S S O T HE RW IS E NO T E D.
S E AT IN G P L AN E
0.20 M AX
D ET AIL A
Figure 28. 352-Lead metric Plastic Ball Grid Array (PBGA) (B-352) ORDERING GUIDE
A complete modem requires the device listed in Table 19 plus a software solution as described in MODEM SOFTWARE on page 2.
Table 19. Ordering Guide Part Number Ambient Temperature Range Instruction Rate Package Description Package Option
ADSP-21MOD980N-000
0C to +70C
80 MHz
352-Ball PBGA
B-352
42
6/2001 REV. PrB

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